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- Battery lifetime estimation for LoRaWAN communicationsPublication . Fialho, Vitor; Fortes, FernandoSmart Cities concept increased the number of end devices (ED) which allow the acquisition of parameters for further analysis and processing. The actual technologies based on Internet of Things (IoT) enable sensors connectivity to Internet. This feature allows real time acquisition of several physical data important for smart cities monitoring. In order to minimize the power consumption, Low Power Wide Area Networks (LPWAN) assumes an important role on the evolution and growing of wireless network sensors. In this particular type of network, LoRaWAN has taken the lead, among other technologies. Typically most end devices need to be powered with batteries, since they are in remote zones. Therefore one important issue to consider is the global power consumption of the end device building blocks: LoRa transceiver, microcontroller unit and sensor unit. This paper presents the study and simulation results supported on LoRa modulation parameters, in order to estimate the battery lifetime, which is useful for IoT remote sensing units. The achieved results denote it is possible to configure LoRa transceiver with similar parameters and different payloads, reaching the same battery lifetime.
- A 5GHz1.8V low power CMOS low-noise amplifierPublication . Azevedo, Fernando; Mendes, Luís; Fialho, Vitor; Vaz, João C.; Fortes, Fernando; Rosário, Maria J.Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.
- Wireless communication based on chirp signals for LoRa IoT DevicesPublication . Fialho, Vitor; Azevedo, FernandoThis paper presents the study of chirp signals for wireless communications between Internet of Thing devices used on low power wide area networks. Up and down chirp concept is introduced as well as the chirp spread spectrum concept. A computationally efficient symbol decoding method is presented based of discrete Fourier transform as an alternative to typical coherent detection. The proposed LoRa simulation model is implemented in MATLAB allowing the communication system evaluation based on bit error rate and packet error rate.
- A 5GHz/1.8V CMOS active balun integrated with LNAPublication . Azevedo, Fernando; Mendes, Luís; Fialho, Vitor; Vaz, João C.; Fortes, Fernando; Rosário, Maria J.The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.
- Integer N synthesizer design for LoRa transceiversPublication . Fialho, VitorThis paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz.
- Oscilador LC monolítico comandado por tensão a 2,4GHzPublication . Fialho, Vitor; Barreto, Ricardo; Fortes, FernandoEsta Comunicação tem como finalidade divulgar o projecto de um VCO monolítico a 2.4GHz para integrar uma Malha de Captura de Fase (PLL). O Oscilador projectado é baseado num par diferencial cruzado (parte activa). O circuito funciona com uma tensão de 2.8V e com uma tensão de comando entre 1.6V e 1.8V, produzindo uma variação de frequência entre 2.4GHz e 2.75GHz.
- Local oscillator phase noise model for EVM estimation and optimizationPublication . Fialho, Vitor; Fortes, Fernando; Vieira, ManuelaThis work presents a local oscillator (LO) phase noise model and its experimental validation for carrier to phase noise ratio (CPNR) and error vector magnitude (EVM) evaluation on a radio frequency (RF) transceiver. The proposed LO model is based on a type II charge pump phase locked loop with a combined phase noise source from the voltage controlled oscillator and input reference with a low pass characteristic. The obtained results of CPNR and signal to phase noise ratio are based on numerical simulations and validated with experimental measurements based on a commercial RF transceiver chip. The EVM of the transmitted RF channel is also measured and compared with CPNR.
- Misturador monolítico a 2.4GHz em tecnologia CMOS 0.35μm usando célula de GilbertPublication . Barreto, Ricardo; Fialho, Vitor; Fortes, FernandoEsta comunicação visa apresentar um misturador duplamente equilibrado monolítico, para operar a 2.4 GHz, em tecnologia CMOS de 0.35μm usando como topologia básica a célula de Gilbert. O misturador apresentado destina-se a funcionar como detector de fase numa Malha de Captura de Fase (PLL). O circuito utiliza transístores MOS e foi inicialmente projectado como misturador de dois sinais sinusoidais, analisando-se o ganho como misturador e a rejeição de espúrias na saída para verificar o funcionamento como circuito equilibrado. Seguidamente foi testado como detector de fase, apresentando na sua saída um sinal de erro proporcional à diferença de fase entre os dois sinais de entrada. No desenho e simulação de desempenho do circuito utilizou-se o ambiente CADENCE, uma ferramenta de desenvolvimento de circuitos integrados bastante versátil, e o design-kit da Austria Micro Systems. A tecnologia utilizada é a CMOS standard de 0.35μm (C35B4) com 4 metais e 2 polys.