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- Driving scheme using MIS photosensor for luminance control of AMOLED pixelPublication . Vygranenko, Yuri; Fernandes, Miguel; Sazonov, Andrei; Vieira, ManuelaThis paper presents a new driving scheme utilizing an in-pixel metal-insulator-semiconductor (MIS) photosensor for luminance control of active-matrix organic light-emitting diode (AMOLED) pixel. The proposed 3-TFT circuit is controlled by an external driver performing the signal readout, processing, and programming operations according to a luminance adjusting algorithm. To maintain the fabrication simplicity, the embedded MIS photosensor shares the same layer stack with pixel TFTs. Performance characteristics of the MIS structure with a nc-Si : H/a-Si : H bilayer absorber were measured and analyzed to prove the concept. The observed transient dark current is associated with charge trapping at the insulator-semiconductor interface that can be largely eliminated by adjusting the bias voltage during the refresh cycle. Other factors limiting the dynamic range and external quantum efficiency are also determined and verified using a small-signal model of the device. Experimental results demonstrate the feasibility of the MIS photosensor for the discussed driving scheme.
- Photo-induced instability of nanocrystalline silicon TFTsPublication . Bauza, Marius; Ahnood, Arman; Li, Flora; Vygranenko, Yuri; Esmaeili-Rad, Mohammad R.; Chaji, G.; Sazonov, Andrei; Robertson, John; Milne, William; Nathan, ArokiaWe examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift (Delta V-T) after 6 h of bias stress is about 7 times larger in the case with illumination than in the dark. Under bias stress alone, the primary instability mechanism is charge trapping at the semiconductor/insulator interface. In contrast, under combined bias-and-light stress, the prevailing mechanism appears to be the creation of defect states in the channel, and believed to take place in the amorphous phase, where the increase in the electron density induced by electrical bias enhances the non-radiative recombination of photo-excited electron-hole pairs. The results reported here are consistent with observations of photo-induced efficiency degradation in solar cells.
- Characterization of a-Si:H solar cell modules on plastic substrates by high resolution LBIC techniquePublication . Fernandes, Miguel; Vygranenko, Yuri; Vieira, Manuela; Sazonov, Andrei; Yang, R.; Khosropour, A.This article reports on characterization of hydrogenated amorphous silicon (a-Si:H) photovoltaic modules fabricated on 100 mu m thick PEN plastic films. Experimental results show that the shunt leakage is one of the factors reducing the device performance. Current-voltage characteristics of individual a-Si:H p-i-n cells were analysed to estimate a variation of shunt resistances. A SPICE model of the a-Si:H p-i-n cell with local shunt leakage was also developed to analyse the impact of leakage currents on the device performance. Using the LBIC technique, the presence of multiple shunts in the cell was detected. They are attributed to surface defects in plastic foils, which are thermally induced during the device fabrication. (C) 2015 Published by Elsevier Ltd.
- Amorphous silicon photovoltaic modules on flexible plastic substratesPublication . Vygranenko, Yuri; Fernandes, Miguel; Louro, Paula; Vieira, Manuela; Khosropour, Alireza; Yang, Ruifeng; Sazonov, AndreiThis paper reports on a monolithic 10 cm x 10 cm area PV module integrating an array of 72 a-Si:H n-i-p cells on a 100 mu m thick polyethylene-naphtalate substrate. The n-i-p stack is deposited using a PECVD system at 150 degrees C substrate temperature. The design optimization and device performance analysis are performed using a two-dimensional distributed circuit model of the photovoltaic cell. The circuit simulator SPICE is used to calculate current and potential distributions in a network of sub-cell circuits, and also to map Joule losses in the front TCO electrode and the metal grid. Experimental results show that the shunt leakage is one of the factors reducing the device performance. Current-voltage characteristics of individual a-Si: H p-i-n cells were analyzed to estimate a variation of shunt resistances. Using the LBIC technique, the presence of multiple shunts in the n-i-p cell was detected. To understand the nature of electrical shunts, the change in the surface roughness of all device layers was analyzed throughout fabrication process. It is found that surface defects in plastic foils, which are thermally induced during the device fabrication, form microscopic pinholes filled with highly conductive top electrode material.