Publication
High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs
| dc.contributor.author | Dias, Tiago | |
| dc.contributor.author | Roma, Nuno | |
| dc.contributor.author | Sousa, Leonel | |
| dc.date.accessioned | 2014-05-27T15:08:50Z | |
| dc.date.available | 2014-05-27T15:08:50Z | |
| dc.date.issued | 2013-10 | |
| dc.description.abstract | A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps). | por |
| dc.identifier.citation | DIAS, Tiago; ROMA, Nuno; LEONEL, Sousa - High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs. Design and Architectures for Signal and Image Processing (DASIP). (2013), p. 14-21. | por |
| dc.identifier.uri | http://hdl.handle.net/10400.21/3583 | |
| dc.language.iso | eng | por |
| dc.peerreviewed | yes | por |
| dc.publisher | IEEE | por |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6661512&tag=1 | por |
| dc.subject | Video coding | por |
| dc.subject | AVC / HEVC | por |
| dc.subject | Integer DCT | por |
| dc.subject | Multistandard architecture | por |
| dc.subject | Systolic array | por |
| dc.subject | FPGA | por |
| dc.title | High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs | por |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Cagliari | por |
| oaire.citation.endPage | 21 | por |
| oaire.citation.startPage | 14 | por |
| oaire.citation.title | Conference 2013 Design and Architectures for Signal and Image Processing (DASIP) | por |
| person.familyName | Braga da Silva Dias | |
| person.givenName | Tiago Miguel | |
| person.identifier | 709056 | |
| person.identifier.ciencia-id | E21C-1E42-EE73 | |
| person.identifier.orcid | 0000-0001-7445-5823 | |
| person.identifier.rid | H-4265-2011 | |
| person.identifier.scopus-author-id | 11540058800 | |
| rcaap.rights | restrictedAccess | por |
| rcaap.type | conferenceObject | por |
| relation.isAuthorOfPublication | 1c03cd27-cf61-43fb-803c-19885a82d62a | |
| relation.isAuthorOfPublication.latestForDiscovery | 1c03cd27-cf61-43fb-803c-19885a82d62a |
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