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Advisor(s)
Abstract(s)
Deep learning and, in particular, convolutional neural networks (CNN) achieve very good results on several computer vision applications like security and surveillance, where image and video analysis are required. These networks are quite demanding in terms of computation and memory and therefore are usually implemented in high-performance computing platforms or devices. Running CNNs in embedded platforms or devices with low computational and memory resources requires a careful optimization of system architectures and algorithms to obtain very efficient designs. In this context, Field Programmable Gate Arrays (FPGA) can achieve this efficiency since the programmable hardware fabric can be tailored for each specific network. In this paper, a very efficient configurable architecture for CNN inference targeting any density FPGAs is described. The architecture considers fixed-point arithmetic and image batch to reduce computational, memory and memory bandwidth requirements without compromising network accuracy. The developed architecture supports the execution of large CNNs in any FPGA devices including those with small on-chip memory size and logic resources. With the proposed architecture, it is possible to infer an image in AlexNet in 4.3 ms in a ZYNQ7020 and 1.2 ms in a ZYNQ7045.
Description
Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2016 do Instituto Politécnico de Lisboa. Código de referência IPL/2019/inCNeuraINet_ISEL
Keywords
Deep learning Convolutional neural network Smart edge devices FPGA
Citation
VÉSTIAS, Mário P.; [et al] – A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 77 (2020), pp. 1-15
Publisher
Elsevier