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Advisor(s)
Abstract(s)
Financial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation.
Description
Keywords
Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA
Citation
VÉSTIAS, Mário Pereira; NETO, Horácio – Improving the area of fast parallel decimal multipliers. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 61 (2018), pp. 96-107
Publisher
Elsevier