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Improving the area of fast parallel decimal multipliers

dc.contributor.authorVéstias, Mário
dc.contributor.authorCláudio de Campos Neto, Horácio
dc.date.accessioned2018-06-06T10:11:35Z
dc.date.available2018-06-06T10:11:35Z
dc.date.issued2018-05-22
dc.description.abstractFinancial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationVÉSTIAS, Mário Pereira; NETO, Horácio – Improving the area of fast parallel decimal multipliers. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 61 (2018), pp. 96-107pt_PT
dc.identifier.doi10.1016/j.micpro.2018.05.015pt_PT
dc.identifier.issn0141-9331
dc.identifier.urihttp://hdl.handle.net/10400.21/8571
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherElsevierpt_PT
dc.relation.publisherversionhttps://reader.elsevier.com/reader/sd/0A56C2AB19001063818476223579D4222E8DCCA75AFFD9A419D0C70B97FAAEF471D620A8B6B9933148FFC07F767AE88Apt_PT
dc.subjectDecimal multiplicationpt_PT
dc.subjectParallel multiplicationpt_PT
dc.subjectExcess-6 codingpt_PT
dc.subject5221 codingpt_PT
dc.subjectFPGApt_PT
dc.titleImproving the area of fast parallel decimal multiplierspt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/3599-PPCDT/PEst-OE%2FEEI%2FLA0021%2F2013/PT
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/3599-PPCDT/PTDC%2FEEA-ELC%2F122098%2F2010/PT
oaire.citation.endPage107pt_PT
oaire.citation.startPage96pt_PT
oaire.citation.titleMicroprocessors and Microsystemspt_PT
oaire.citation.volume61
oaire.fundingStream3599-PPCDT
oaire.fundingStream3599-PPCDT
person.familyNameVéstias
person.familyNameCláudio de Campos Neto
person.givenNameMário
person.givenNameHorácio
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.ciencia-id9915-3BDF-5C35
person.identifier.orcid0000-0001-8556-4507
person.identifier.orcid0000-0002-3621-8322
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsclosedAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublication38334d5e-83e8-494c-a9e0-396299376d97
relation.isAuthorOfPublication.latestForDiscoverya7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isProjectOfPublicationfd214540-11d6-49e2-a7cd-462eab6a3fb1
relation.isProjectOfPublicationad249e8f-da84-49e0-a916-86abe607bafa
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