Publication
Improving the area of fast parallel decimal multipliers
dc.contributor.author | Véstias, Mário | |
dc.contributor.author | Cláudio de Campos Neto, Horácio | |
dc.date.accessioned | 2018-06-06T10:11:35Z | |
dc.date.available | 2018-06-06T10:11:35Z | |
dc.date.issued | 2018-05-22 | |
dc.description.abstract | Financial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation. | pt_PT |
dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
dc.identifier.citation | VÉSTIAS, Mário Pereira; NETO, Horácio – Improving the area of fast parallel decimal multipliers. Microprocessors and Microsystems. ISSN 0141-9331. Vol. 61 (2018), pp. 96-107 | pt_PT |
dc.identifier.doi | 10.1016/j.micpro.2018.05.015 | pt_PT |
dc.identifier.issn | 0141-9331 | |
dc.identifier.uri | http://hdl.handle.net/10400.21/8571 | |
dc.language.iso | eng | pt_PT |
dc.peerreviewed | yes | pt_PT |
dc.publisher | Elsevier | pt_PT |
dc.relation.publisherversion | https://reader.elsevier.com/reader/sd/0A56C2AB19001063818476223579D4222E8DCCA75AFFD9A419D0C70B97FAAEF471D620A8B6B9933148FFC07F767AE88A | pt_PT |
dc.subject | Decimal multiplication | pt_PT |
dc.subject | Parallel multiplication | pt_PT |
dc.subject | Excess-6 coding | pt_PT |
dc.subject | 5221 coding | pt_PT |
dc.subject | FPGA | pt_PT |
dc.title | Improving the area of fast parallel decimal multipliers | pt_PT |
dc.type | journal article | |
dspace.entity.type | Publication | |
oaire.awardURI | info:eu-repo/grantAgreement/FCT/3599-PPCDT/PEst-OE%2FEEI%2FLA0021%2F2013/PT | |
oaire.awardURI | info:eu-repo/grantAgreement/FCT/3599-PPCDT/PTDC%2FEEA-ELC%2F122098%2F2010/PT | |
oaire.citation.endPage | 107 | pt_PT |
oaire.citation.startPage | 96 | pt_PT |
oaire.citation.title | Microprocessors and Microsystems | pt_PT |
oaire.citation.volume | 61 | |
oaire.fundingStream | 3599-PPCDT | |
oaire.fundingStream | 3599-PPCDT | |
person.familyName | Véstias | |
person.familyName | Cláudio de Campos Neto | |
person.givenName | Mário | |
person.givenName | Horácio | |
person.identifier.ciencia-id | 4717-C2C7-3F2C | |
person.identifier.ciencia-id | 9915-3BDF-5C35 | |
person.identifier.orcid | 0000-0001-8556-4507 | |
person.identifier.orcid | 0000-0002-3621-8322 | |
person.identifier.rid | H-9953-2012 | |
person.identifier.scopus-author-id | 14525867300 | |
project.funder.identifier | http://doi.org/10.13039/501100001871 | |
project.funder.identifier | http://doi.org/10.13039/501100001871 | |
project.funder.name | Fundação para a Ciência e a Tecnologia | |
project.funder.name | Fundação para a Ciência e a Tecnologia | |
rcaap.rights | closedAccess | pt_PT |
rcaap.type | article | pt_PT |
relation.isAuthorOfPublication | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 | |
relation.isAuthorOfPublication | 38334d5e-83e8-494c-a9e0-396299376d97 | |
relation.isAuthorOfPublication.latestForDiscovery | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 | |
relation.isProjectOfPublication | fd214540-11d6-49e2-a7cd-462eab6a3fb1 | |
relation.isProjectOfPublication | ad249e8f-da84-49e0-a916-86abe607bafa | |
relation.isProjectOfPublication.latestForDiscovery | fd214540-11d6-49e2-a7cd-462eab6a3fb1 |