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A many-core co-processor for embedded parallel computing on FPGA

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dc.contributor.authorJosé, Wilson
dc.contributor.authorNeto, Horácio
dc.contributor.authorVéstias, Mário
dc.date.accessioned2016-04-18T15:18:58Z
dc.date.available2016-04-18T15:18:58Z
dc.date.issued2015
dc.description.abstractSingle processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.pt_PT
dc.identifier.citationJOSÉ, Wilson; [et al] - A many-core co-processor for embedded parallel computing on FPGA. In 18th Euromicro Conference on Digital System Design (DSD). Funchal, Portugal: IEEE, 2015. ISBN 978-1-4673-8035-5. Pp. 539-542pt_PT
dc.identifier.doi10.1109/DSD.2015.23pt_PT
dc.identifier.isbn978-1-4673-8035-5
dc.identifier.urihttp://hdl.handle.net/10400.21/6014
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherIEEE - Institute of Electrical and Electronics Engineers Inc.pt_PT
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7302321&tag=1pt_PT
dc.subjectMany-corept_PT
dc.subjectFPGApt_PT
dc.subjectMatrix multiplicationpt_PT
dc.subjectParallel processingpt_PT
dc.subjectReconfigurable computingpt_PT
dc.titleA many-core co-processor for embedded parallel computing on FPGApt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceFunchal, Portugalpt_PT
oaire.citation.endPage542pt_PT
oaire.citation.startPage539pt_PT
oaire.citation.titleDSD 2015, Euromicro Conference on Digital System Designpt_PT
person.familyNameVéstias
person.givenNameMário
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.orcid0000-0001-8556-4507
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublication.latestForDiscoverya7d22b29-c961-45ac-bc09-cd5e1002f1e8

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