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Authors
Advisor(s)
Abstract(s)
Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.
Description
Keywords
Many-core FPGA Matrix multiplication Parallel processing Reconfigurable computing
Citation
JOSÉ, Wilson; [et al] - A many-core co-processor for embedded parallel computing on FPGA. In 18th Euromicro Conference on Digital System Design (DSD). Funchal, Portugal: IEEE, 2015. ISBN 978-1-4673-8035-5. Pp. 539-542
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.