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Authors
Advisor(s)
Abstract(s)
In this paper, a configurable many-core hardware/
software architecture is proposed to efficiently execute the
widely known and commonly used K-means clustering algorithm.
A prototype was designed and implemented on a Xilinx Zynq-
7000 All Programmable SoC. A single core configured with the
slowest configuration achieves a 10X speed-up compared to the
software only solution. The system is fully scalable and capable
of achieving much higher speed-ups by increasing its parallelism.
Description
Keywords
Clustering K-means Hardware/Software Co-design Hardware acceleration Systems on Chip
Citation
CANILHO, José; VÉSTIAS, Mário Pereira; NETO, Horácio - Multi-core for k-means clustering on FPGA. In 26th International Conference on Field-Programmable Logic and Applications (FPL). Lausanne, Switzerland: IEEE, 2016. ISSN 1946-1488. Pp. 1-4
Publisher
Institute of Electrical and Electronics Engineers