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Decimal addition on FPGA based on a mixed BCD/excess-6 representation

2017-11Artigo científico Acesso restrito
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dc.contributor.authorNeto, Horácio
dc.contributor.authorVéstias, Mário
dc.date.accessioned2018-01-31T12:01:27Z
dc.date.available2018-01-31T12:01:27Z
dc.date.issued2017-11
dc.description.abstractDecimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationNETO, Horácio; VÉSTIAS, Mário – Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocessors and Microsystems. ISSN: 0141-9331. Vol. 55 (2017), pp. 91-99pt_PT
dc.identifier.doihttps://doi.org/10.1016/j.micpro.2017.10.004pt_PT
dc.identifier.issn0141-9331
dc.identifier.urihttp://hdl.handle.net/10400.21/7999
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherElsevierpt_PT
dc.relation.publisherversionhttps://ac.els-cdn.com/S0141933116303908/1-s2.0-S0141933116303908-main.pdf?_tid=d97d2814-067c-11e8-9c61-00000aab0f01&acdnat=1517399573_017310743971b9dc7e7f48001933a313pt_PT
dc.subjectDecimal additionpt_PT
dc.subjectParallel additionpt_PT
dc.subjectBinary/decimal additionpt_PT
dc.subjectMultioperand additionpt_PT
dc.subjectExcess-6 codingpt_PT
dc.subjectFPGApt_PT
dc.titleDecimal addition on FPGA based on a mixed BCD/excess-6 representationpt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardNumberUID/CEC/50021/2013
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/5876/UID%2FCEC%2F50021%2F2013/PT
oaire.citation.endPage99pt_PT
oaire.citation.startPage91pt_PT
oaire.citation.titleMicroprocessors and Microsystemspt_PT
oaire.citation.volume55pt_PT
oaire.fundingStream5876
person.familyNameVéstias
person.givenNameMário
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.orcid0000-0001-8556-4507
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsclosedAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublication.latestForDiscoverya7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isProjectOfPublication9964a800-3334-42d6-aab0-1f8870cbe7b1
relation.isProjectOfPublication.latestForDiscovery9964a800-3334-42d6-aab0-1f8870cbe7b1

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