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Autores
Orientador(es)
Resumo(s)
Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.
Descrição
Palavras-chave
Decimal addition Parallel addition Binary/decimal addition Multioperand addition Excess-6 coding FPGA
Contexto Educativo
Citação
NETO, Horácio; VÉSTIAS, Mário – Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocessors and Microsystems. ISSN: 0141-9331. Vol. 55 (2017), pp. 91-99
Editora
Elsevier