Fully parameterizable VLSI architecture for sub-pixel motion estimation with low memory bandwidth requirements

Dias, Tiago; Roma, Nuno; Sousa, Leonel

http://hdl.handle.net/10400.21/8773

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Authors

Dias, Tiago

Roma, Nuno

Sousa, Leonel

Abstract(s)

This paper proposes a new scalable and efficient VLSI type-II architecture for real-time motion estimation optimized for subpel refinement algorithms. Based on the proposed architecture, which provides minimum latency, maximum throughput, and full utilization of the hardware resources, the implementation of a dedicated motion estimation coprocessor is also presented in this paper. This circuit is characterized by low memory bandwidth requirements, a modular and highly flexible structure and is capable of estimating motion vectors with half-pixel accuracy using the bilinear interpolation algorithm. Experimental results for implementations on ASIC and FPGA devices show that by using the proposed architecture it is possible to estimate motion vectors up to the 16CIF image format in real-time, with any given sub-pixel accuracy.

Keywords

VLSI Architecture Sub-pixel motion Bandwidth

URI

http://hdl.handle.net/10400.21/8773

Citation

DIAS, Tiago; ROMA, Nuno; SOUSA, Leonel – Fully parameterizable VLSI architecture for sub-pixel motion estimation with low memory bandwidth requirements. In JETC05 - Jornadas de Engenharia de Eletrónica e Telecomunicações e de Computadores. Lisboa, Portugal: ISEL – Instituto Superior de Engenharia de Lisboa, 2005. Pp. 1-6