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Authors
Advisor(s)
Abstract(s)
A conventional flash analog-to-digital converter (ADC) with a Wallace tree encoder ensures monotonicity and avoids missing codes, but still requires comparators with low offset voltage, which implies high area and power consumption. In this paper, we extend the purpose of this flash implementation, to allow the comparators to have extremely high offset voltages. This leads to a new approach toward the design of a flash ADC that does not require any type of calibration, allow easy porting among technologies and benefits from scaling. A statistical study is presented to demonstrate the effectiveness of the new method, and a modification is proposed to ensure full-range operation. It is shown that a proposed N-bit ADC has a performance equivalent to an (N−m)(N−m)-bit conventional flash ADC, with considerable gains in area and power consumption, with less design effort. The design flow of the OST ADC, with the necessary steps, is presented. A circuit, employing minimum dimension transistors, was fabricated in 0.13-μmμm CMOS and used as a proof of concept for the ADCs proposed here.
Description
Keywords
Analog–digital conversion Flash ADC Wallace tree Stochastic errors Offset voltage
Citation
COUTO-PINTO, António; FERNANDES, Jorge R.; PIEDADE, Moisés; SILVA, Manuel M. - A flash ADC tolerant to high offset voltage comparators. Circuits Systems and Signal Processing. ISSN 0278-081X. Vol. 36, N. º 3 (2017), pp. 1150–1168
Publisher
Springer Verlag