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FPGA implementation of IEEE 802.15.3C receiver

dc.contributor.authorVéstias, Mário
dc.contributor.authorSarmento, Helena
dc.date.accessioned2015-09-07T13:42:44Z
dc.date.available2015-09-07T13:42:44Z
dc.date.issued2012
dc.description.abstractThis paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.por
dc.identifier.citationVÉSTIAS, Mário Pereira; SARMENTO, Helena – FPGA implementation of IEEE 802.15.3C receiver. In IEEE 16Th International Symposium on Consumer Electronics (ISCE). IEEE, 2012. ISBN: 978-1-4673-1356-8por
dc.identifier.isbn978-1-4673-1356-8
dc.identifier.urihttp://hdl.handle.net/10400.21/5083
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherIEEEpor
dc.titleFPGA implementation of IEEE 802.15.3C receiverpor
dc.typeconference object
dspace.entity.typePublication
oaire.citation.titleBook Series: IEEE International Symposium on Consumer Electronicspor
person.familyNameVéstias
person.givenNameMário
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.orcid0000-0001-8556-4507
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
rcaap.rightsclosedAccesspor
rcaap.typeconferenceObjectpor
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublication.latestForDiscoverya7d22b29-c961-45ac-bc09-cd5e1002f1e8

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