Publication
Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA
| dc.contributor.author | Rodrigues, Tiago | |
| dc.contributor.author | Véstias, Mário | |
| dc.date.accessioned | 2016-04-18T15:34:11Z | |
| dc.date.available | 2016-04-18T15:34:11Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution. | pt_PT |
| dc.identifier.citation | RODRIGUES, Tiago; VÉSTIAS, Mário - Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA. 18th Euromicro Conference on Digital System Design (DSD). Funchal, Portugal: IEEE, 2015. ISBN 978-1-4673-8035-5. Pp. 65-71 | pt_PT |
| dc.identifier.doi | 10.1109/DSD.2015.31 | pt_PT |
| dc.identifier.isbn | 978-1-4673-8035-5 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/6016 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. | pt_PT |
| dc.subject | Dynamic reconfiguration | pt_PT |
| dc.subject | FPGA | pt_PT |
| dc.subject | JPEG decoder | pt_PT |
| dc.title | Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Funchal, Portugal | pt_PT |
| oaire.citation.endPage | 71 | pt_PT |
| oaire.citation.startPage | 65 | pt_PT |
| oaire.citation.title | DSD 2015, Euromicro Conference on Digital System Design | pt_PT |
| person.familyName | Véstias | |
| person.givenName | Mário | |
| person.identifier.ciencia-id | 4717-C2C7-3F2C | |
| person.identifier.orcid | 0000-0001-8556-4507 | |
| person.identifier.rid | H-9953-2012 | |
| person.identifier.scopus-author-id | 14525867300 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
| relation.isAuthorOfPublication | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 | |
| relation.isAuthorOfPublication.latestForDiscovery | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 |
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