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Exploring data size to run convolutional neural networks in low density FPGAs

dc.contributor.authorGonçalves, Ana
dc.contributor.authorPeres, Tiago
dc.contributor.authorVéstias, Mário
dc.date.accessioned2019-05-30T09:33:47Z
dc.date.available2019-05-30T09:33:47Z
dc.date.issued2019-03-29
dc.descriptionEste trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2018 do Instituto Politécnico de Lisboa. Código de referência IPL/2018/LiteCNN_ISEL
dc.description.abstractConvolutional Neural Networks (CNNs) obtain very good results in several computer vision applications at the cost of high computational and memory requirements. Therefore, CNN typically run on high performance platforms. However, CNNs can be very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication and real-time decisions turning these systems into smart sensors. In this paper, we explore data quantization for fast CNN inference in low density FPGAs. We redesign LiteCNN, an architecture for real-time inference of large CNN in low density FPGAs, to support hybrid quantization. We study the impact of quantization over the area, performance and accuracy of LiteCNN. LiteCNN with improved quantization of activations and weights improves the best state of the art results for CNN inference in low density FPGAs. With our proposal, it is possible to infer an image in AlexNet in 7.4 ms in a ZYNQ7020 and in 14.8 ms in a ZYNQ7010 with 3% accuracy degradation. Other delay versus accuracy ratios were identified permitting the designer to choose the most appropriate.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationGONÇALVES, Ana; PERES, Tiago; VÉSTIAS, Mário – Exploring data size to run convolutional neural networks in low density FPGAs. In ARC 2019: Applied Reconfigurable Computing – 15th International Symposium on Applied Reconfigurable Computing. Darmstadt, Germany: Springer, 2019. ISBN 978-3-030-17226-8. Pp. 387-401pt_PT
dc.identifier.doihttps://doi.org/10.1007/978-3-030-17227-5_27pt_PT
dc.identifier.isbn978-3-030-17226-8
dc.identifier.isbn978-3-030-17227-5
dc.identifier.urihttp://hdl.handle.net/10400.21/10094
dc.language.isoengpt_PT
dc.publisherSpringerpt_PT
dc.relationUID/CEC/50021/2019 - FCTpt_PT
dc.relationProjeto financiado no âmbito do Concurso de Projetos de Investigação, Desenvolvimento, Inovação & Criação Artística (IDI&CA) financiados pelo Instituto Politécnico de Lisboa. IPL/2018/LiteCNN_ISELpt_PT
dc.subjectConvolutional Neural Networkpt_PT
dc.subjectFPGApt_PT
dc.subjectData quantizationpt_PT
dc.titleExploring data size to run convolutional neural networks in low density FPGAspt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceApril 9-11, 2019 - Darmstadt, Germanypt_PT
oaire.citation.endPage401pt_PT
oaire.citation.startPage387pt_PT
oaire.citation.title15th International Symposium on Applied Reconfigurable Computingpt_PT
person.familyNameGonçalves
person.familyNamePeres
person.familyNameVéstias
person.givenNameAna
person.givenNameTiago
person.givenNameMário
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.orcid0000-0002-0512-7487
person.identifier.orcid0000-0003-1771-4934
person.identifier.orcid0000-0001-8556-4507
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublicationcbca2f8e-c6dd-4b42-b6bc-cb15615da927
relation.isAuthorOfPublicationa96251a8-e95d-4e78-91c3-16e951a9df78
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublication.latestForDiscoverycbca2f8e-c6dd-4b42-b6bc-cb15615da927

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