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Advisor(s)
Abstract(s)
Convolutional Neural Networks (CNNs) obtain very good results in several computer vision applications at the cost of high computational and memory requirements. Therefore, CNN typically run on high performance platforms. However, CNNs can be very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication and real-time decisions turning these systems into smart sensors. In this paper, we explore data quantization for fast CNN inference in low density FPGAs. We redesign LiteCNN, an architecture for real-time inference of large CNN in low density FPGAs, to support hybrid quantization. We study the impact of quantization over the area, performance and accuracy of LiteCNN. LiteCNN with improved quantization of activations and weights improves the best state of the art results for CNN inference in low density FPGAs. With our proposal, it is possible to infer an image in AlexNet in 7.4 ms in a ZYNQ7020 and in 14.8 ms in a ZYNQ7010 with 3% accuracy degradation. Other delay versus accuracy ratios were identified permitting the designer to choose the most appropriate.
Description
Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2018 do Instituto Politécnico de Lisboa. Código de referência IPL/2018/LiteCNN_ISEL
Keywords
Convolutional Neural Network FPGA Data quantization
Citation
GONÇALVES, Ana; PERES, Tiago; VÉSTIAS, Mário – Exploring data size to run convolutional neural networks in low density FPGAs. In ARC 2019: Applied Reconfigurable Computing – 15th International Symposium on Applied Reconfigurable Computing. Darmstadt, Germany: Springer, 2019. ISBN 978-3-030-17226-8. Pp. 387-401
Publisher
Springer