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Decimal multiplication in FPGA with a novel decimal adder/subtractor

2021-06-29Journal article Open access
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dc.contributor.authorVéstias, Mário
dc.contributor.authorNeto, Horácio C
dc.date.accessioned2021-10-07T12:56:03Z
dc.date.available2021-10-07T12:56:03Z
dc.date.issued2021-06-29
dc.description.abstractFinancial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationVÉSTIAS, Mário P.; NETO, Horácio C. – Decimal multiplication in FPGA with a novel decimal adder/subtractor. Algorithms. eISSN 1999-4893. Vol. 14, N.º 7 (2021), pp. 1-21pt_PT
dc.identifier.doi10.3390/a14070198pt_PT
dc.identifier.eissn1999-4893
dc.identifier.urihttp://hdl.handle.net/10400.21/13833
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherMDPIpt_PT
dc.relationInstituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa
dc.subjectDecimal multiplicationpt_PT
dc.subjectDecimal adder parallel multiplicationpt_PT
dc.subjectExcess-3 codingpt_PT
dc.subjectFPGApt_PT
dc.titleDecimal multiplication in FPGA with a novel decimal adder/subtractorpt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardTitleInstituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F50021%2F2020/PT
oaire.citation.endPage21pt_PT
oaire.citation.issue7pt_PT
oaire.citation.startPage1pt_PT
oaire.citation.titleAlgorithmspt_PT
oaire.citation.volume14pt_PT
oaire.fundingStream6817 - DCRRNI ID
person.familyNameVéstias
person.familyNameCláudio de Campos Neto
person.givenNameMário
person.givenNameHorácio
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.ciencia-id9915-3BDF-5C35
person.identifier.orcid0000-0001-8556-4507
person.identifier.orcid0000-0002-3621-8322
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
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relation.isAuthorOfPublication38334d5e-83e8-494c-a9e0-396299376d97
relation.isAuthorOfPublication.latestForDiscovery38334d5e-83e8-494c-a9e0-396299376d97
relation.isProjectOfPublication1f3e7ad3-87bb-4203-919b-53592c18fcea
relation.isProjectOfPublication.latestForDiscovery1f3e7ad3-87bb-4203-919b-53592c18fcea

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