Browsing by Issue Date, starting with "2021-06-29"
Now showing 1 - 2 of 2
Results Per Page
Sort Options
- 3D antenna characterization for WPT applicationsPublication . Jordão, Marina; Pires, Diogo; Belo, Daniel; Pinho, Pedro; Carvalho, Nuno BorgesThe main goal of this paper is to present a three-dimensional (3D) antenna array to improve the performance of wireless power transmission (WPT) systems, as well as its characterization with over-the-air (OTA) multi-sine techniques. The 3D antenna consists of 15 antenna elements attached to an alternative 3D structure, allowing energy to be transmitted to all azimuth directions at different elevation angles without moving. The OTA multi-sine characterization technique was first utilized to identify issues in antenna arrays. However, in this work, the technique is used to identify which elements of the 3D antenna should operate to transmit the energy in a specific direction. Besides, the 3D antenna design description and its characterization are performed to authenticate its operation. Since 3D antennas are an advantage in WPT applications, the antenna is evaluated in a real WPT scenario to power an RF-DC converter, and experimental results are presented.
- Decimal multiplication in FPGA with a novel decimal adder/subtractorPublication . Véstias, Mário; Neto, Horácio CFinancial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.