Publication
Sparse matrix multiplication on a reconfigurable many-core architecture
| dc.contributor.author | Pinhão, João | |
| dc.contributor.author | José, Wilson | |
| dc.contributor.author | Neto, Horácio | |
| dc.contributor.author | Véstias, Mário | |
| dc.date.accessioned | 2016-04-18T15:27:21Z | |
| dc.date.available | 2016-04-18T15:27:21Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs. | pt_PT |
| dc.identifier.citation | PINHÃO, João; [et al] - Sparse matrix multiplication on a reconfigurable many-core architecture. In 18th Euromicro Conference on Digital System Design (DSD). Funchal, Portugal: IEEE, 2015. ISBN 978-1-4673-8035-5. Pp. 330-336 | pt_PT |
| dc.identifier.doi | 10.1109/DSD.2015.89 | pt_PT |
| dc.identifier.isbn | 978-1-4673-8035-5 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/6015 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | IEEE-Institute Electrical Electronics Engineers INC | pt_PT |
| dc.subject | Sparse matrix | pt_PT |
| dc.subject | FPGA | pt_PT |
| dc.subject | Many-core | pt_PT |
| dc.subject | Matrix multiplication | pt_PT |
| dc.title | Sparse matrix multiplication on a reconfigurable many-core architecture | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Funchal, Portugal | pt_PT |
| oaire.citation.endPage | 336 | pt_PT |
| oaire.citation.startPage | 330 | pt_PT |
| oaire.citation.title | DSD 2015, Euromicro Conference on Digital System Design | pt_PT |
| person.familyName | Véstias | |
| person.givenName | Mário | |
| person.identifier.ciencia-id | 4717-C2C7-3F2C | |
| person.identifier.orcid | 0000-0001-8556-4507 | |
| person.identifier.rid | H-9953-2012 | |
| person.identifier.scopus-author-id | 14525867300 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
| relation.isAuthorOfPublication | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 | |
| relation.isAuthorOfPublication.latestForDiscovery | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 |
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