Publication
High performance IP core for HEVC quantization
| dc.contributor.author | Dias, Tiago | |
| dc.contributor.author | Roma, Nuno | |
| dc.contributor.author | Sousa, Leonel | |
| dc.date.accessioned | 2019-02-18T12:22:10Z | |
| dc.date.available | 2019-02-18T12:22:10Z | |
| dc.date.issued | 2015-07-30 | |
| dc.description.abstract | A new class of quantization architectures suitable for the realization of high performance and hardware efficient forward, inverse and unified quantizers for HEVC is presented. The proposed structures are based on a highly flexible and optimized integer datapath that can be configured to provide several pipelined and non-pipelined implementations, offering distinct trade-offs between performance and hardware cost, which makes them highly suitable for most video coding application domains. The experimental results obtained using a 90 nm CMOS process show that the proposed class of quantization architectures is able to process 4k UHDTV video sequences in real-time (3840 x 2160 @ 30fps), with a power consumption as low as 3.9 mW when the unified architecture is operated at 374 MHz. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.citation | DIAS, Tiago; ROMA, Nuno; SOUSA, Leonel – High performance IP core for HEVC quantization. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). Lisbon, Portugal, 2015. ISBN 978-1-4799-8391-9. Pp. 2828-2831 | pt_PT |
| dc.identifier.doi | 10.1109/ISCAS.2015.7169275 | pt_PT |
| dc.identifier.isbn | 978-1-4799-8391-9 | |
| dc.identifier.issn | 0271-4302 | |
| dc.identifier.issn | 2158-1525 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/9519 | |
| dc.language.iso | eng | pt_PT |
| dc.publisher | Institute of Electrical and Electronics Engineers | pt_PT |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7169275 | pt_PT |
| dc.subject | High performance | pt_PT |
| dc.subject | Hardware efficient | pt_PT |
| dc.title | High performance IP core for HEVC quantization | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.awardURI | info:eu-repo/grantAgreement/FCT/5876/UID%2FCEC%2F50021%2F2013/PT | |
| oaire.citation.conferencePlace | 24-27 May 2015 - Lisbon, Portugal | pt_PT |
| oaire.citation.endPage | 2831 | pt_PT |
| oaire.citation.startPage | 2828 | pt_PT |
| oaire.citation.title | 2015 IEEE International Symposium on Circuits and Systems (ISCAS) | pt_PT |
| oaire.fundingStream | 5876 | |
| person.familyName | Braga da Silva Dias | |
| person.familyName | Roma | |
| person.familyName | Sousa | |
| person.givenName | Tiago Miguel | |
| person.givenName | Nuno | |
| person.givenName | Leonel | |
| person.identifier | 709056 | |
| person.identifier.ciencia-id | E21C-1E42-EE73 | |
| person.identifier.ciencia-id | CB11-EDBA-7BA5 | |
| person.identifier.orcid | 0000-0001-7445-5823 | |
| person.identifier.orcid | 0000-0003-2491-4977 | |
| person.identifier.orcid | 0000-0002-8066-221X | |
| person.identifier.rid | H-4265-2011 | |
| person.identifier.rid | B-2749-2009 | |
| person.identifier.scopus-author-id | 11540058800 | |
| person.identifier.scopus-author-id | 7004775548 | |
| project.funder.identifier | http://doi.org/10.13039/501100001871 | |
| project.funder.name | Fundação para a Ciência e a Tecnologia | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
| relation.isAuthorOfPublication | 1c03cd27-cf61-43fb-803c-19885a82d62a | |
| relation.isAuthorOfPublication | 8bf85aaa-28df-4d94-95c8-353bd018af9c | |
| relation.isAuthorOfPublication | 07c59d8c-0469-4df6-b96f-60ac362d7712 | |
| relation.isAuthorOfPublication.latestForDiscovery | 07c59d8c-0469-4df6-b96f-60ac362d7712 | |
| relation.isProjectOfPublication | 9964a800-3334-42d6-aab0-1f8870cbe7b1 | |
| relation.isProjectOfPublication.latestForDiscovery | 9964a800-3334-42d6-aab0-1f8870cbe7b1 |