Advisor(s)
Abstract(s)
A new class of quantization architectures suitable for the realization of high performance and hardware efficient forward, inverse and unified quantizers for HEVC is presented. The proposed structures are based on a highly flexible and optimized integer datapath that can be configured to provide several pipelined and non-pipelined implementations, offering distinct trade-offs between performance and hardware cost, which makes them highly suitable for most video coding application domains. The experimental results obtained using a 90 nm CMOS process show that the proposed class of quantization architectures is able to process 4k UHDTV video sequences in real-time (3840 x 2160 @ 30fps), with a power consumption as low as 3.9 mW when the unified architecture is operated at 374 MHz.
Description
Keywords
High performance Hardware efficient
Citation
DIAS, Tiago; ROMA, Nuno; SOUSA, Leonel – High performance IP core for HEVC quantization. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). Lisbon, Portugal, 2015. ISBN 978-1-4799-8391-9. Pp. 2828-2831
Publisher
Institute of Electrical and Electronics Engineers