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Coarse-grained reconfigurable computing with the versat architecture

dc.contributor.authorD. Lopes, João
dc.contributor.authorVéstias, Mário
dc.contributor.authorDuarte, Rui Policarpo
dc.contributor.authorNeto, Horácio C
dc.contributor.authorDe Sousa, Jose
dc.date.accessioned2021-04-22T15:13:30Z
dc.date.available2021-04-22T15:13:30Z
dc.date.issued2021-03
dc.description.abstractReconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationLOPES, João D.; [et al] – Coarse-grained reconfigurable computing with the versat architecture. Electronics. Vol. 10, N.º 6 (2021), pp. 1-23pt_PT
dc.identifier.doi10.3390/electronics10060669pt_PT
dc.identifier.eissn2079-9292
dc.identifier.urihttp://hdl.handle.net/10400.21/13224
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherMDPIpt_PT
dc.relationUIDB/50021/2020 - FCTpt_PT
dc.subjectReconfigurable computingpt_PT
dc.subjectCoarse-grained reconfigurable arrayspt_PT
dc.subjectHeterogeneous systemspt_PT
dc.subjectLow power systemspt_PT
dc.titleCoarse-grained reconfigurable computing with the versat architecturept_PT
dc.typejournal article
dspace.entity.typePublication
oaire.citation.endPage23pt_PT
oaire.citation.issue6pt_PT
oaire.citation.startPage1pt_PT
oaire.citation.titleElectronicspt_PT
oaire.citation.volume10pt_PT
person.familyNameD. Lopes
person.familyNameVéstias
person.familyNameDuarte
person.familyNameCláudio de Campos Neto
person.familyNamede Sousa
person.givenNameJoão
person.givenNameMário
person.givenNameRui
person.givenNameHorácio
person.givenNameJose
person.identifier.ciencia-id8E19-37E3-AF01
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.ciencia-idB91E-770F-19A3
person.identifier.ciencia-id9915-3BDF-5C35
person.identifier.ciencia-idBE18-E262-E0EC
person.identifier.orcid0000-0002-8903-9715
person.identifier.orcid0000-0001-8556-4507
person.identifier.orcid0000-0002-7060-4745
person.identifier.orcid0000-0002-3621-8322
person.identifier.orcid0000-0001-7525-7546
person.identifier.ridH-9953-2012
person.identifier.ridI-4402-2015
person.identifier.ridL-6859-2015
person.identifier.scopus-author-id14525867300
person.identifier.scopus-author-id24823991600
person.identifier.scopus-author-id7102813024
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublication404c2df1-70ec-48c9-b5ad-a6fa5700fb35
relation.isAuthorOfPublicationa7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isAuthorOfPublicationf2b4b9e6-6c89-48c7-bc83-62d2e98a787b
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relation.isAuthorOfPublication.latestForDiscoveryd98a4d45-2d45-42ec-9f1d-14775723709b

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