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Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

2014-07Journal article Restricted access
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dc.contributor.authorDias, Tiago
dc.contributor.authorRoma, Nuno
dc.contributor.authorSousa, Leonel
dc.date.accessioned2015-08-19T10:14:36Z
dc.date.available2015-08-19T10:14:36Z
dc.date.issued2014-07
dc.description.abstractA unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.por
dc.identifier.citationDIAS, Tiago Miguel Braga da Silva; ROMA, Nuno; SOUSA, Leonel – Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs. Eurasip Journal on Advances in Signal Processing. ISSN: 1687-6180. (2014), Art. nr. 108.
dc.identifier.issn1687-6180
dc.identifier.urihttp://hdl.handle.net/10400.21/4844
dc.language.isoengen
dc.peerreviewedyespor
dc.publisherSpringer International Publishing AGpor
dc.relationSFRH/PROTEC/50152/2009
dc.relationStrategic Project - LA 21 - 2013-2014
dc.relation.ispartofseries108
dc.subjectVideo Codingpor
dc.subjectMulti-Standardpor
dc.subjectTransform Architecturepor
dc.subjectSystolic Arraypor
dc.subjectFPGApor
dc.titleUnified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecspor
dc.typejournal article
dspace.entity.typePublication
oaire.awardTitleStrategic Project - LA 21 - 2013-2014
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/PEst-OE%2FEEI%2FLA0021%2F2013/PT
oaire.citation.conferencePlaceChampor
oaire.citation.titleEurasip Journal on Advances in Signal Processingpor
oaire.fundingStream6817 - DCRRNI ID
person.familyNameBraga da Silva Dias
person.givenNameTiago Miguel
person.identifier709056
person.identifier.ciencia-idE21C-1E42-EE73
person.identifier.orcid0000-0001-7445-5823
person.identifier.ridH-4265-2011
person.identifier.scopus-author-id11540058800
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsclosedAccesspor
rcaap.typearticlepor
relation.isAuthorOfPublication1c03cd27-cf61-43fb-803c-19885a82d62a
relation.isAuthorOfPublication.latestForDiscovery1c03cd27-cf61-43fb-803c-19885a82d62a
relation.isProjectOfPublicationc57bd42b-bb65-4368-b331-6c6b646fd0e9
relation.isProjectOfPublication.latestForDiscoveryc57bd42b-bb65-4368-b331-6c6b646fd0e9

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