Publication
Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system
| dc.contributor.author | Miguens Matutino, Pedro | |
| dc.contributor.author | Araújo, Juvenal | |
| dc.contributor.author | Sousa, Leonel | |
| dc.contributor.author | Chaves, Ricardo | |
| dc.date.accessioned | 2018-05-08T09:32:32Z | |
| dc.date.available | 2018-05-08T09:32:32Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | In this paper a novel pipelined FPGA coprocessor for ECC is proposed, exploiting the parallelism capabilities of RNS to the computation of large operand algorithms. This intrinsic characteristic of representing large integer numbers as a set of smaller and independent values allows for the parallelization of the computationally heavy large operand multiplications, required in asymmetrical cryptographic algorithms. Towards a compact and performance efficient design, the RNS coprocessor supports a single highly pipelined multi-modulo arithmetic unit. Implementation results, on FPGA of this RNS based ECC coprocessor, suggest one of the smallest programmable designs with a proportional performance when compared with related state of the art. Additionally, the resulting architecture allows for the computation of varying key sizes without changing the design or its implementation. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.citation | MATUTINO, Pedro Miguens, [et al] – Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system. IEEE. ISBN 978-1-5386-3437-0. (2017), pp. 261-268. | pt_PT |
| dc.identifier.isbn | 978-1-5386-3437-0 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/8488 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Institute of Electrical and Electronics Engineers | pt_PT |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8344638 | pt_PT |
| dc.subject | FPGA | pt_PT |
| dc.subject | Coprocessor | pt_PT |
| dc.subject | RNS | pt_PT |
| dc.title | Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.awardURI | info:eu-repo/grantAgreement/FCT/5876/UID%2FCEC%2F50021%2F2013/PT | |
| oaire.citation.endPage | 268 | pt_PT |
| oaire.citation.startPage | 261 | pt_PT |
| oaire.fundingStream | 5876 | |
| person.familyName | Miguens Matutino | |
| person.givenName | Pedro | |
| person.identifier.ciencia-id | 851D-A88F-2F71 | |
| person.identifier.orcid | 0000-0001-6518-1306 | |
| project.funder.identifier | http://doi.org/10.13039/501100001871 | |
| project.funder.name | Fundação para a Ciência e a Tecnologia | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | article | pt_PT |
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