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Fault-tolerant design of three-phase dual-buck VSI topologies

2019-12-09Conference object Restricted access
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dc.contributor.authorCordeiro, Armando
dc.contributor.authorFernao Pires, Vitor
dc.contributor.authorSilva, J. Fernando
dc.date.accessioned2019-12-13T11:19:09Z
dc.date.available2019-12-13T11:19:09Z
dc.date.issued2019-12-09
dc.description.abstractThis paper presents fault tolerant topologies for the three-phase dual-buck voltage-source inverter (VSI). Using the proposed topologies, increased reliability is obtained, which is fundamental in many safety-critical applications. The solutions intend to achieve fast changing between main and redundant branches through the combination of several power devices. The present study focuses on solutions that can be used to replace the classical two-level three-phase voltage-source inverters to extend the fault-tolerant capacity. Several aspects of failure modes, detection and isolation processes within power electronic converters are discussed regarding the requirements of safety related applications. The theoretical validity of the proposed solution is confirmed by simulation results.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationCORDEIRO, Armando; PIRES, V. Fernão; SILVA, J. Fernando – Fault-tolerant design of three-phase dual-buck VSI topologies. In IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society. Lisbon, Portugal: IEEE, 2019. ISBN 978-1-7281-4878-6. Pp. 4630-4635pt_PT
dc.identifier.doi10.1109/IECON.2019.8927183pt_PT
dc.identifier.isbn978-1-7281-4878-6
dc.identifier.isbn978-1-7281-4879-3
dc.identifier.issn2577-1647
dc.identifier.issn1553-572X
dc.identifier.urihttp://hdl.handle.net/10400.21/10856
dc.language.isoengpt_PT
dc.publisherInstitute of Electrical and Electronics Engineerspt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8927183pt_PT
dc.subjectDual-buck inverterpt_PT
dc.subjectReliabilitypt_PT
dc.subjectFault-tolerantpt_PT
dc.subjectInverter failurept_PT
dc.subjectFailure modespt_PT
dc.titleFault-tolerant design of three-phase dual-buck VSI topologiespt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlace14-17 Oct. 2019 - Lisbon, Portugalpt_PT
oaire.citation.endPage4635pt_PT
oaire.citation.startPage4630pt_PT
oaire.citation.titleIECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Societypt_PT
person.familyNameCordeiro
person.familyNameFernao Pires
person.givenNameArmando
person.givenNameVitor
person.identifier2692732
person.identifier1017494
person.identifier.ciencia-idEE1F-34B0-4A02
person.identifier.ciencia-idDC1C-D708-69C5
person.identifier.orcid0000-0001-6658-5783
person.identifier.orcid0000-0002-3764-0955
person.identifier.ridL-6836-2015
person.identifier.scopus-author-id7003305269
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublicationcb166065-fd85-42f7-88b5-a835226f38a1
relation.isAuthorOfPublication2891ab5a-f371-44ac-8d28-f49a8c3efabd
relation.isAuthorOfPublication.latestForDiscovery2891ab5a-f371-44ac-8d28-f49a8c3efabd

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