| Name: | Description: | Size: | Format: | |
|---|---|---|---|---|
| 199.73 KB | Adobe PDF |
Authors
Advisor(s)
Abstract(s)
This paper describes the hardware implementation of a High-Rate MIMO Receiver in an FPGA for three modulations, namely BPSK, QPSK and 16-QAM based on the Alamouti scheme. The implementation with 16-QAM achieves more than 1.6 Gbps with 66% of the resources of a medium-sized Virtex-4 FPGA. This results indicate that the Alamouti scheme is a good design option for hardware implementation of a high-rate MIMO receiver. Also, using an FPGA, the modulation can be dynamically changed on demand.
Description
Keywords
Citation
PINHO, Pedro; VÉSTIAS, Mário Pereira – A high-rate mimo receiver in an FPGA. In IEEE Antennas and Propagation Society International Symposium (APSURSI), Book Series: IEEE Antennas and Propagation Society International Symposium, 2012. IEEE, 2012. ISBN: 978-1-4673-0462-7