Publication
Efficient design of pruned convolutional neural networks on FPGA
| dc.contributor.author | Véstias, Mário | |
| dc.date.accessioned | 2020-11-20T13:07:05Z | |
| dc.date.available | 2020-11-20T13:07:05Z | |
| dc.date.issued | 2020-11-14 | |
| dc.description | Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2020 do Instituto Politécnico de Lisboa. Código de referência IPL/2020/TRAINEE/ISEL | |
| dc.description.abstract | Convolutional Neural Networks (CNNs) have improved several computer vision applications, like object detection and classification, when compared to other machine learning algorithms. Running these models in edge computing devices close to data sources is attracting the attention of the community since it avoids high-latency data communication of private data for cloud processing and permits real-time decisions turning these systems into smart embedded devices. Running these models is computationally very demanding and requires a large amount of memory, which are scarce in edge devices compared to a cloud center. In this paper, we proposed an architecture for the inference of pruned convolutional neural networks in any density FPGAs. A configurable block pruning method is proposed together with an architecture that supports the efficient execution of pruned networks. Also, pruning and batching are studied together to determine how they influence each other. With the proposed architecture, we run the inference of a CNN with an average performance of 322 GOPs for 8-bit data in a XC7Z020 FPGA. The proposed architecture running AlexNet processes 240 images/s in a ZYNQ7020 and 775 images/s in a ZYNQ7045 with only 1.2% accuracy degradation. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.citation | VÉSTIAS, Mário – Efficient design of pruned convolutional neural networks on FPGA. Journal of Signal Processing Systems for Signal Image and Video Technology. ISSN 1939-8115. Vol. 93, N.º 5 (SI), (2020), pp. 531-544 | pt_PT |
| dc.identifier.issn | 1939-8115 | |
| dc.identifier.issn | 1939-8018 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/12388 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Springer | pt_PT |
| dc.relation | UIDB/50021/2020 - FCT | pt_PT |
| dc.relation | Projeto financiado no âmbito do Concurso de Projetos de Investigação, Desenvolvimento, Inovação & Criação Artística (IDI&CA) financiados pelo Instituto Politécnico de Lisboa. IPL/2020/TRAINEE/ISEL | pt_PT |
| dc.relation.publisherversion | https://link.springer.com/article/10.1007/s11265-020-01606-2 | |
| dc.subject | Deep learning | pt_PT |
| dc.subject | Convolutional neural network | pt_PT |
| dc.subject | FPGA | pt_PT |
| dc.subject | Block pruning | pt_PT |
| dc.subject | Edge computing | pt_PT |
| dc.title | Efficient design of pruned convolutional neural networks on FPGA | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.citation.endPage | 544 | pt_PT |
| oaire.citation.issue | 5 | |
| oaire.citation.startPage | 531 | pt_PT |
| oaire.citation.title | Journal of Signal Processing Systems for Signal Image and Video Technology | pt_PT |
| oaire.citation.volume | 93 | |
| person.familyName | Véstias | |
| person.givenName | Mário | |
| person.identifier.ciencia-id | 4717-C2C7-3F2C | |
| person.identifier.orcid | 0000-0001-8556-4507 | |
| person.identifier.rid | H-9953-2012 | |
| person.identifier.scopus-author-id | 14525867300 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | article | pt_PT |
| relation.isAuthorOfPublication | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 | |
| relation.isAuthorOfPublication.latestForDiscovery | a7d22b29-c961-45ac-bc09-cd5e1002f1e8 |
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