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Autores
Orientador(es)
Resumo(s)
In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The overlay was evaluated with matrix multiplication, LU decomposition and Fast-Fourier Transform (FFT) on a ZYNQ-7020 FPGA platform. The results show that using a system-level many-core overlay avoids complex hardware design and still provides good performance results.
Descrição
Palavras-chave
Many-core overlay High-performance Sobreposição de núcleos Alta performance
Contexto Educativo
Citação
VÉSTIAS, Mário; NETO, Horácio – A many-core overlay for high performance embedded computing on FPGAS. In 1st International Workshop on FPGAs for Software Programmers (FSP 2014). Munich, Germany: 2014. Pp. 71-76