Publication
Faster convolutional neural networks in low density FPGAs using block pruning
| dc.contributor.author | Peres, Tiago | |
| dc.contributor.author | Gonçalves, Ana | |
| dc.contributor.author | Véstias, Mário | |
| dc.date.accessioned | 2019-05-30T08:44:27Z | |
| dc.date.available | 2019-05-30T08:44:27Z | |
| dc.date.issued | 2019-03-29 | |
| dc.description | Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2018 do Instituto Politécnico de Lisboa. Código de referência IPL/2018/LiteCNN_ISEL | |
| dc.description.abstract | Convolutional Neural Networks (CNNs) are achieving promising results in several computer vision applications. Running these models is computationally very intensive and needs a large amount of memory to store weights and activations. Therefore, CNN typically run on high performance platforms. However, the classification capabilities of CNNs are very useful in many applications running in embedded platforms close to data production since it avoids data communication for cloud processing and permits real-time decisions turning these systems into smart embedded systems. In this paper, we improve the inference of large CNN in low density FPGAs using pruning. We propose block pruning and apply it to LiteCNN, an architecture for CNN inference that achieves high performance in low density FPGAs. With the proposed LiteCNN optimizations, we have an architecture for CNN inference with an average performance of 275 GOPs for 8-bit data in a XC7Z020 FPGA. With our proposal, it is possible to infer an image in AlexNet in 5.1 ms in a ZYNQ7020 and in 13.2 ms in a ZYNQ7010 with only 2.4% accuracy degradation. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.citation | PERES, Tiago; GONÇALVES, Ana; VÉSTIAS, Mário – Faster convolutional neural networks in low density FPGAs using block pruning. In ARC 2019: Applied Reconfigurable Computing – 15th International Symposium on Applied Reconfigurable Computing. Darmstadt, Germany: Springer, 2019. ISBN 978-3-030-17226-8. Pp. 402-416 | pt_PT |
| dc.identifier.doi | https://doi.org/10.1007/978-3-030-17227-5_28 | pt_PT |
| dc.identifier.isbn | 978-3-030-17226-8 | |
| dc.identifier.isbn | 978-3-030-17227-5 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/10093 | |
| dc.language.iso | eng | pt_PT |
| dc.publisher | Springer | pt_PT |
| dc.relation | UID/CEC/50021/2019 - FCT | pt_PT |
| dc.relation | Projeto financiado no âmbito do Concurso de Projetos de Investigação, Desenvolvimento, Inovação & Criação Artística (IDI&CA) financiados pelo Instituto Politécnico de Lisboa. IPL/2018/LiteCNN_ISEL | pt_PT |
| dc.subject | Convolutional Neural Network | pt_PT |
| dc.subject | FPGA | pt_PT |
| dc.subject | Block pruning | pt_PT |
| dc.title | Faster convolutional neural networks in low density FPGAs using block pruning | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | April 9-11, 2019 - Darmstadt, Germany | pt_PT |
| oaire.citation.endPage | 416 | pt_PT |
| oaire.citation.startPage | 402 | pt_PT |
| oaire.citation.title | 15th International Symposium on Applied Reconfigurable Computing | pt_PT |
| person.familyName | Peres | |
| person.familyName | Gonçalves | |
| person.familyName | Véstias | |
| person.givenName | Tiago | |
| person.givenName | Ana | |
| person.givenName | Mário | |
| person.identifier.ciencia-id | 4717-C2C7-3F2C | |
| person.identifier.orcid | 0000-0003-1771-4934 | |
| person.identifier.orcid | 0000-0002-0512-7487 | |
| person.identifier.orcid | 0000-0001-8556-4507 | |
| person.identifier.rid | H-9953-2012 | |
| person.identifier.scopus-author-id | 14525867300 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
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