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Parallel dot-products for deep learning on FPGA

dc.contributor.authorVéstias, Mário
dc.contributor.authorDuarte, Rui
dc.contributor.authorDe Sousa, Jose
dc.contributor.authorCláudio de Campos Neto, Horácio
dc.date.accessioned2019-04-01T10:16:29Z
dc.date.available2019-04-01T10:16:29Z
dc.date.issued2017-10-05
dc.description.abstractDeep neural networks have recently shown great results in a vast set of image applications. The associated deep learning models are computationally very demanding and, therefore, several hardware solutions have been proposed to accelerate their computation. FPGAs have recently shown very good performances for these kind of applications and so it is considered a promising platform to accelerate the execution of deep learning algorithms. A common operation in these algorithms is multiply-accumulate (MACC) that is used to calculate dot-products. Since many dot products can be calculated in parallel, as long as memory bandwidth is available, it is very important to implement this operation very efficiently to increase the density of MACC units in an FPGA. In this paper, we propose an implementation of parallel MACC units in FPGA for dot-product operations with very high performance/area ratios using a mix of DSP blocks and LUTs. We consider fixed-point representations with 8 bits of size, but the method can be applied to other bit widths. The method allows us to achieve TOPs performances, even for low cost FPGAs.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationVÉSTIAS, Mário; [et al] – Parallel dot-products for deep learning on FPGA. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). Ghent, Belgium: IEEE, 2017. ISBN 978-9-0903-0428-1. Pp. 1-4pt_PT
dc.identifier.doi10.23919/FPL.2017.8056863pt_PT
dc.identifier.isbn978-9-0903-0428-1
dc.identifier.isbn978-1-5386-2040-3
dc.identifier.issn1946-1488
dc.identifier.urihttp://hdl.handle.net/10400.21/9807
dc.language.isoengpt_PT
dc.publisherInstitute of Electrical and Electronics Engineerspt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8056863pt_PT
dc.subjectMultiply-accumulatept_PT
dc.subjectDeep learningpt_PT
dc.subjectFPGApt_PT
dc.subjectMultiplicar-acumularpt_PT
dc.titleParallel dot-products for deep learning on FPGApt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/5876/UID%2FCEC%2F50021%2F2013/PT
oaire.citation.conferencePlace4-8 Sept. 2017 - Ghent, Belgiumpt_PT
oaire.citation.endPage4pt_PT
oaire.citation.startPage1pt_PT
oaire.citation.title27th International Conference on Field Programmable Logic and Applications (FPL)pt_PT
oaire.fundingStream5876
person.familyNameVéstias
person.familyNameDuarte
person.familyNamede Sousa
person.familyNameCláudio de Campos Neto
person.givenNameMário
person.givenNameRui
person.givenNameJose
person.givenNameHorácio
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.ciencia-idB91E-770F-19A3
person.identifier.ciencia-idBE18-E262-E0EC
person.identifier.ciencia-id9915-3BDF-5C35
person.identifier.orcid0000-0001-8556-4507
person.identifier.orcid0000-0002-7060-4745
person.identifier.orcid0000-0001-7525-7546
person.identifier.orcid0000-0002-3621-8322
person.identifier.ridH-9953-2012
person.identifier.ridI-4402-2015
person.identifier.ridL-6859-2015
person.identifier.scopus-author-id14525867300
person.identifier.scopus-author-id24823991600
person.identifier.scopus-author-id7102813024
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
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relation.isAuthorOfPublicationf2b4b9e6-6c89-48c7-bc83-62d2e98a787b
relation.isAuthorOfPublicationd98a4d45-2d45-42ec-9f1d-14775723709b
relation.isAuthorOfPublication38334d5e-83e8-494c-a9e0-396299376d97
relation.isAuthorOfPublication.latestForDiscoveryd98a4d45-2d45-42ec-9f1d-14775723709b
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