Repository logo
 
No Thumbnail Available
Publication

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

Use this identifier to reference this record.

Advisor(s)

Abstract(s)

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

Description

Keywords

Switch linearization Reliability Switched-capacitor linearization control circuit (SLC) Bootstrapped switch Clock boosting

Citation

Galhardo Acácio, Goes J., Paulino N. Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies. Analog Integrated Circuits and Signal Processing. 2010; 64 (1): 13-22 Sp. Iss.

Research Projects

Organizational Units

Journal Issue

Publisher

Springer

CC License