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Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

2014-10Conference object Restricted access
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dc.contributor.authorJosé, Wilson
dc.contributor.authorSilva, Ana Rita
dc.contributor.authorNeto, Horácio
dc.contributor.authorVéstias, Mário
dc.date.accessioned2015-08-18T10:42:28Z
dc.date.available2015-08-18T10:42:28Z
dc.date.issued2014-10
dc.description.abstractThis paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).por
dc.identifier.citationJOSÉ, Wilson; [et al] – Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. In FPL 2014 Conference Digest - 24th International Conference on Field Programmable Logic and Applications. New York : IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. ISBN: 978-300044645-0. Art. nr. 6927391.
dc.identifier.doi10.1109/FPL.2014.6927391
dc.identifier.isbn978-300044645-0
dc.identifier.urihttp://hdl.handle.net/10400.21/4799
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherIEEE - Institute of Electrical and Electronics Engineers Inc.por
dc.relationPTDC/EEAELC/122098/2010
dc.relationStrategic Project - LA 21 - 2013-2014
dc.relation.ispartofseries6927391
dc.subjectDigital Arithmeticpor
dc.subjectField Programmable Gate Arrays (FPGA)por
dc.subjectProgram Processorspor
dc.subjectEfficient Implementationpor
dc.subjectFloating-Point Arithmeticpor
dc.subjectFloatingpointpor
dc.subjectFused Multiply-Addpor
dc.subjectRelative Performancepor
dc.subjectResource Usagepor
dc.subjectSingle Precisionpor
dc.subjectSquare-Rootpor
dc.titleEfficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGApor
dc.typeconference object
dspace.entity.typePublication
oaire.awardTitleStrategic Project - LA 21 - 2013-2014
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/PEst-OE%2FEEI%2FLA0021%2F2013/PT
oaire.citation.conferencePlaceNew Yorkpor
oaire.citation.titleFPL 2014 Conference Digest - 24th International Conference on Field Programmable Logic and Applicationspor
oaire.fundingStream6817 - DCRRNI ID
person.familyNameVéstias
person.givenNameMário
person.identifier.ciencia-id4717-C2C7-3F2C
person.identifier.orcid0000-0001-8556-4507
person.identifier.ridH-9953-2012
person.identifier.scopus-author-id14525867300
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsclosedAccesspor
rcaap.typeconferenceObjectpor
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relation.isAuthorOfPublication.latestForDiscoverya7d22b29-c961-45ac-bc09-cd5e1002f1e8
relation.isProjectOfPublicationc57bd42b-bb65-4368-b331-6c6b646fd0e9
relation.isProjectOfPublication.latestForDiscoveryc57bd42b-bb65-4368-b331-6c6b646fd0e9

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