Publication
Low energy heterogeneous computing with multiple RISC-V and CGRA cores
| dc.contributor.author | Fiolhais, Luís | |
| dc.contributor.author | Gonçalves, Fernando | |
| dc.contributor.author | Duarte, Rui P. | |
| dc.contributor.author | Véstias, Mário | |
| dc.contributor.author | Sousa, Jose T. De | |
| dc.date.accessioned | 2019-05-09T08:47:11Z | |
| dc.date.available | 2019-05-09T08:47:11Z | |
| dc.date.issued | 2019-05-01 | |
| dc.description.abstract | The idea of combining multiple CPU and CGRA cores is not in itself original but detailed characterizations of such architectures and measurements on compelling applications are difficult to find in the literature. Although commercial CPUs, GPUs and FPGAs are widely available, there are no commercial CGRAs, which may be attributed to the lack of metrics on performance, energy and cost. In this paper, we introduce a heterogeneous computing platform consisting of several RISC-V CPU and Versat CGRA cores. Implementation results for several instances of the architecture are presented. The CPU of choice is the promising open source RISC-V architecture, which has never been featured in CPU/CGRA architectures. This paper presents independent implementations of two RISC-V cores: a minimal one, useful as a simple controller, and a more performant 5-stage pipeline implementation. The RISC-V cores have been designed using the recent Chisel HDL, useful for automating tasks pertaining to the writing of RTL. The selected CGRA is the published Versat architecture, for which 4 different instances have been created. Implementation results for 2 FPGA families and ASIC technology nodes are presented: area, frequency and power. Applications cover digital audio and machine learning, demonstrating the versatility of the proposed platform at competitive area, frequency and energy footprints. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.citation | FIOLHAIS, Luís; [et al] – Low energy heterogeneous computing with multiple RISC-V and CGRA cores. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Sapporo, Japan: IEEE, 2019. ISBN 978-1-7281-0397-6. Pp. 1-5 | pt_PT |
| dc.identifier.doi | 10.1109/ISCAS.2019.8702538 | pt_PT |
| dc.identifier.isbn | 978-1-7281-0397-6 | |
| dc.identifier.isbn | 978-1-7281-0398-3 | |
| dc.identifier.issn | 2158-1525 | |
| dc.identifier.issn | 0271-4302 | |
| dc.identifier.uri | http://hdl.handle.net/10400.21/9965 | |
| dc.language.iso | eng | pt_PT |
| dc.publisher | Institute of Electrical and Electronics Engineers | pt_PT |
| dc.relation | PTDC/EEI-HAC/30848/2017 - FCT | pt_PT |
| dc.relation | UID/CEC/50021/2019 - FCT | pt_PT |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8702538 | pt_PT |
| dc.subject | Low power architectures | pt_PT |
| dc.subject | RISC-V | pt_PT |
| dc.subject | CGRAs | pt_PT |
| dc.subject | Heterogeneous computing | pt_PT |
| dc.title | Low energy heterogeneous computing with multiple RISC-V and CGRA cores | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | 26-29 May 2019 - Sapporo, Japan | pt_PT |
| oaire.citation.endPage | 5 | pt_PT |
| oaire.citation.startPage | 1 | pt_PT |
| oaire.citation.title | 2019 IEEE International Symposium on Circuits and Systems (ISCAS) | pt_PT |
| person.familyName | Véstias | |
| person.familyName | de Sousa | |
| person.givenName | Mário | |
| person.givenName | Jose | |
| person.identifier.ciencia-id | 4717-C2C7-3F2C | |
| person.identifier.ciencia-id | BE18-E262-E0EC | |
| person.identifier.orcid | 0000-0001-8556-4507 | |
| person.identifier.orcid | 0000-0001-7525-7546 | |
| person.identifier.rid | H-9953-2012 | |
| person.identifier.rid | L-6859-2015 | |
| person.identifier.scopus-author-id | 14525867300 | |
| person.identifier.scopus-author-id | 7102813024 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
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