Rodrigues, TiagoVéstias, Mário2016-04-182016-04-182015RODRIGUES, Tiago; VÉSTIAS, Mário - Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA. 18th Euromicro Conference on Digital System Design (DSD). Funchal, Portugal: IEEE, 2015. ISBN 978-1-4673-8035-5. Pp. 65-71978-1-4673-8035-5http://hdl.handle.net/10400.21/6016Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution.engDynamic reconfigurationFPGAJPEG decoderconference object10.1109/DSD.2015.31