José, WilsonSilva, Ana RitaNeto, HorácioVéstias, Mário2015-08-182015-08-182014-10JOSÉ, Wilson; [et al] – Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. In FPL 2014 Conference Digest - 24th International Conference on Field Programmable Logic and Applications. New York : IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. ISBN: 978-300044645-0. Art. nr. 6927391.978-300044645-0http://hdl.handle.net/10400.21/4799This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).engDigital ArithmeticField Programmable Gate Arrays (FPGA)Program ProcessorsEfficient ImplementationFloating-Point ArithmeticFloatingpointFused Multiply-AddRelative PerformanceResource UsageSingle PrecisionSquare-Rootconference object10.1109/FPL.2014.6927391