Utilize este identificador para referenciar este registo: http://hdl.handle.net/10400.21/702
Título: Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies
Autor: Galhardo, Acácio João
Goes, J.
Paulino, N.
Palavras-chave: Switch linearization
Reliability
Switched-capacitor linearization control circuit (SLC)
Bootstrapped switch
Clock boosting
Data: Jul-2010
Editora: Springer
Citação: Galhardo Acácio, Goes J., Paulino N. Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies. Analog Integrated Circuits and Signal Processing. 2010; 64 (1): 13-22 Sp. Iss.
Relatório da Série N.º: 1
Resumo: This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.
Peer review: yes
URI: http://hdl.handle.net/10400.21/702
ISSN: 0925-1030
Aparece nas colecções:ISEL - Eng. Electrotécn. - Artigos



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