Utilize este identificador para referenciar este registo: http://hdl.handle.net/10400.21/4799
Título: Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA
Autor: José, Wilson
Silva, Ana Rita
Neto, Horácio
Véstias, Mário Pereira
Palavras-chave: Digital Arithmetic
Field Programmable Gate Arrays (FPGA)
Program Processors
Efficient Implementation
Floating-Point Arithmetic
Floatingpoint
Fused Multiply-Add
Relative Performance
Resource Usage
Single Precision
Square-Root
Data: Out-2014
Editora: IEEE - Institute of Electrical and Electronics Engineers Inc.
Citação: JOSÉ, Wilson; [et al] – Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. In FPL 2014 Conference Digest - 24th International Conference on Field Programmable Logic and Applications. New York : IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. ISBN: 978-300044645-0. Art. nr. 6927391.
Relatório da Série N.º: 6927391
Resumo: This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).
Peer review: yes
URI: http://hdl.handle.net/10400.21/4799
DOI: 10.1109/FPL.2014.6927391
ISBN: 978-300044645-0
Aparece nas colecções:ISEL - Eng. Elect. Tel. Comp. - Comunicações

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