Utilize este identificador para referenciar este registo: http://hdl.handle.net/10400.21/3583
Título: High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs
Autor: Dias, Tiago
Roma, Nuno
Sousa, Leonel
Palavras-chave: Video coding
AVC / HEVC
Integer DCT
Multistandard architecture
Systolic array
FPGA
Data: Out-2013
Editora: IEEE
Citação: DIAS, Tiago; ROMA, Nuno; LEONEL, Sousa - High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs. Design and Architectures for Signal and Image Processing (DASIP). (2013), p. 14-21.
Resumo: A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).
Peer review: yes
URI: http://hdl.handle.net/10400.21/3583
Versão do Editor: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6661512&tag=1
Aparece nas colecções:ISEL - Eng. Elect. Tel. Comp. - Comunicações

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